Obtain the expressions for times taken for sequential and pipelined execution of
ID: 3822232 • Letter: O
Question
Obtain the expressions for times taken for sequential and pipelined execution of N tasks using a system with M processing stages with an an average time of T_avg at a stage and a maximum time of T_max at any stage, and then show that for an ideal pipeline (i.e., one with no stall) the throughput improvement for infinitely large number of tasks is given by M. T_avg/T_max. Discuss the types of pipeline hazards encountered during a pipelined processing the following 4 sequences of instructions, and the remedial solutions. i) Iw $t1, 4 ($t0); Iw $t2, 8 ($r0); Iw $t3, 12 ($t0); Iw $t4 16 ($t0) ii) add $to, $t1, $t2, ;sub $t5, $t5, $t0 iii) Iw $t0, 8 ($t1); assi $t2, $t0, 45 iv) beq $t0, $t1, label; next: add $t0, $t1, $t2 (and $t0 and $t1 have the same contents).Explanation / Answer
2.
b)
i)
lw $t1,4($t0);
lw $t2,8($t0)
lw $t3,12($t0)
lw $t4,16($t0)
Structural hazard -At the same time,overlap of functional units takes places
ii)
add $t0,$t1,$t2
sub $t5,$t5,$t0
Data hazards - $t0 is sub is fetched before the changes are done
iii)
lw $t0,8($t1)
addi $t2,$t0,45
Data hazards - dependency - $t0 in addi is fetched before the changes are done
iv)
beq $t0,$t1,label
next:
add $t0,$t1,$t2
Control hazard-here PC is changed but it wont be effected till the MEM stage due to which stall occurs
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