Shadow Register Sets a. Describe the use of shadow register sets. b. How many sh

Question

Shadow Register Sets a. Describe the use of shadow register sets. b. How many shadow register sets are supported? c. What instructions are used to move data between them? Floating Point Numbers. We have heretofore focused on integers and characters, but many computing systems need to work with floating point numbers. a. Describe how floating point numbers are represented in the standard IEEE Std 754-2008 b. What is a nan? c. What is a subnormal number? d. Describe the support in the NIOS-II system for IEEE Std 754-2008 floating point operations. Special NIOS-II features and capabilities a. Compare and contrast tightly coupled memory to cache memory. b. What is a custom instruction? How would you use it? c. Describe the difference between Supervisor and User mode. When would you use this capability? Assembly Language Concepts. Consult Appendix B of your textbook to answer these questions. a. Describe the operation of a two-pass assembler b. Describe the operation of a one-pass assembler

Explanation / Answer

1. a) Shadow register is a register devised within the microcontroller for purpose of holding certain data to be used later. Shadow registers are used when we need to modify the read only registers. They help the programmer to keep track of what is written only in registers.

b) When a high-priority interrupt occurs, the processor automatically switches to a shadow register set without software intervention. This reduces overhead in the interrupt handler and reduces effective latency. A hardware solution necessarily has to be finite in terms of the number of shadow register sets in hardware.

For example:

PIC32MX795F512L implements 1 shadow register set.
PIC32MZ2048EFG100 implements 7 shadow register sets.

c) Specific load and store instructions are used to move data between these shadow registers.

2.

a) Floating-point numbers are typically packed into a computer datum as the sign bit, the exponent field, and the significand (mantissa), from left to right. For the IEEE 754 binary formats.

Type Sign Exponent Significand Total bits Exponent bias Bits precision

(IEEE 754-2008) 1 5 10 16 15 11

b) In floating-point calculations, Nan(not a number) is a numeric data type value representing an undefined or unrepresentable value.

A NaN (Not-a-Number) is a symbolic entity encoded in floating-point format. There are two types of NaNs:

Signalling NaN : signals an invalid operation exception.

Quiet NaN : propagates through almost every arithmetic operation without signalling an exception.

c) A subnormal number is a nonzero floating-point number with magnitude less than the magnitude of that format Õs smallest normal number in IEEE 754-2008 framework.

d) A Nios II processor core is a hardware design that implements the Nios II instruction set and supports the functional units described in this floating-point number.

3.

a) Cache memory is implemented with on-chip memory and control logic. Tightly coupled memory is implemented with on-chip memory and a dedicated connection.  A cache uses access patterns to populate data within the cache. It has extra hardware to track the backing address and may have communication with other system entities (SMP) to track when a cache line is dirty. The 'TCM' (tightly coupled memory) is fast, probably SRAM multi-transistor memory, like the cache. Both have a fast dedicated connection to the CPU.

b) Custom instructions give you the ability to tailor the Nios II processor to meet the needs of a particular application. You can accelerate time critical software algorithms by converting them to custom hardware logic blocks.

c) Supervisor mode allows unrestricted operation of the processor. All code has access to all processor instructions and resources. The processor may perform any operation the Nios II architecture provides. Any instruction may be executed, any I/O operation may be initiated, and any area of memory may be accessed.

User mode is available only when the Nios II processor in your hardware design includes an MMU or MPU. User mode exists solely to support operating systems. Only a subset of the instruction set is available in user mode.

4.

a) Two-pass assembler scan the code twice. The first time, just count how long the machine code instructions will be, just to find out the addresses of all the labels. Also, create a table that has a list of all the addresses and where they will be in the program. This table is known as the symbol table. On the second scan, generate the machine code, and use the symbol table to determine how far away jump labels are, and to generate the most efficient instruction.

b) It is a kind of Load-and-go type of assembler that generally generates the object code directly in memory for immediate execution. It parses through your source code only once and complete the process.

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