Suppose we have a computer that uses a memory address word size of 8 bits. This
ID: 3824492 • Letter: S
Question
Suppose we have a computer that uses a memory address word size of 8 bits. This computer has a 16-byte cache with 4 bytes per block. The computer accesses a number of memory locations throughout the course of running a program. Suppose this computer uses direct-mapped cache. The format of a memory address as seen by the cache is shown below: The system accesses memory addresses in this exact order: 0x6E, 0xB9, 0x17, 0xE0, 0x4E, 0x4F, 0x50, 0x91, 0xA8, 0xA9, 0xAB, 0xAD, 0x93, and 0x94. a. What is the hit ratio for the entire memory reference sequence given above, assuming we count the first four accesses as misses? b. What memory blocks will be in the cache after the last address has been accessed?Explanation / Answer
Observation:
We can see that 2 bits are allocated for BLOCK, which indicates that the system consists of (22)4 blocks.
Before we proceed, let us break each memory addresses into TAG, BLOCK, and OFFSET
Add TAG BLOCK OFFSET HIT/MISS
B9 1011 10 01 MISS (compulsory miss)
17 0001 00 01 MISS (compulsory miss)
E0 1110 00 00 MISS (Different tag value)
4E 0100 11 10 MISS (compulsory miss)
4F 0100 11 11 HIT
50 0101 00 00 MISS (Different tag value)
91 1001 00 01 MISS (Different tag value)
A8 1010 10 00 MISS (Different tag value)
A9 1010 10 01 HIT
AB 1010 10 11 HIT
AD 1010 11 01 MISS (Different tag value)
93 1001 00 11 HIT
94 1001 01 00 MISS (compulsory miss)
Hit rate = 4/13 = 0.3077
b.
Cache Status
Block Tag Range (0x)
00 1001 90 - 93
01 1001 94-97
10 1010 A8-AB
11 1010 AC-AF
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