1. A RISC computer having a 1GHZ clock rate executes a program by performing 1.0
ID: 3826127 • Letter: 1
Question
1. A RISC computer having a 1GHZ clock rate executes a program by performing 1.0 x 10^9 instructions having measured CPI of 2 with mix shown in table 1. what is the number of memory accesses performed during the execution of this program?
The answer is 1.35*10^9
But, I don't know why.
2. Computer #1 generates a message and its hash and transmits both via a noisy channel to Computer #2. computer #2 hashes the received message and this hash matches the hash received from computer #1.from this, we can prove that
A. the message was received without error.
B. both the message and the hash were received without error
c. its quite likely that either the message or the hash were received with one or more errors
D. None of the above is correct.
The correct answer is D. But i chose B. why?
Which of the following might be expected to serve as the CSR for an I/O device?
A.memory address 0x00000000 through 0xFFFFFFFF
B.memory address 0x80000000 through 0xF0000000
C.memory address 0x20000000 through 0x2000000F
answer is memory address 0x20000000 through 0x2000000F. but why?
Thank you!
Explanation / Answer
1.
The provided information for the question is insufficient because, the following information is missing:
2.
Computer #1 wants to send a message; hence it generates hash and transmits it to computer #2 via noisy channel. Computer# 2 receives the message and hash from computer #1, and generates hash for the received message. Now, compare the generated hash and received hash from the computer #1. If both are matched, the message is received without error.
But, here computer #2 receives the message via a noisy channel. Therefore there may be a chance to damage or loss of message and hash. Hence, both are received with errors.
Therefore answer is none of the above is correct.
You choose the answer as B, because if no damage or loss of message occurs, the message and hash are received without error.
3.
Memory address 0X2000 0000 through 0X2000 000F is correct. Because, many I/O devices requires, less than 16 Control and Status Registers (CSR).
Therefore, the memory address 0X2000 0000 through 0X2000 000F can represent 16 CSR’s.
Hence, the correct answer is option C.
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