1. Multiple Choice Questions (MCQs), [15 points, 3 points/MCQ] (a) An ALU (Arith

Question

1. Multiple Choice Questions (MCQs), [15 points, 3 points/MCQ] (a) An ALU (Arithmetic Logic Unit) is a —— . i. combinational logic circuit ii. sequential logic circuit iii. none of the above (b) A computer system has a common bus system (constructed using MUXs) for 64 registers of 4-bit each. Each MUX has — select inputs and a total of —- MUX are needed. i. 8, 4 ii. 4, 8 iii. 8, 8 iv. 6, 4 (c) A two-way set associate cache always has a lower miss rate then a direct mapped cache with same block size and total capacity. i. YES – Justification: —- ii. NO – Justification: —- (d) Consider a MIPS processor with 32-bit address bus and cache memory of 1024 words. If a direct mapped cache with one-word block size is used to implement this cache then it has memory word (cache memory word length) of size —- i. 32 bits ii. 20 bits iii. 42 bits iv. 21 bits v. 43 bits (e) A two-way set-associate mapping cache —– hold two memory locations with same set fields. i. can ii. cannot 1. Multiple Choice Questions (MCQs), [15 points, 3 points/MCQ] (a) An ALU (Arithmetic Logic Unit) is a —— . i. combinational logic circuit ii. sequential logic circuit iii. none of the above (b) A computer system has a common bus system (constructed using MUXs) for 64 registers of 4-bit each. Each MUX has — select inputs and a total of —- MUX are needed. i. 8, 4 ii. 4, 8 iii. 8, 8 iv. 6, 4 (c) A two-way set associate cache always has a lower miss rate then a direct mapped cache with same block size and total capacity. i. YES – Justification: —- ii. NO – Justification: —- (d) Consider a MIPS processor with 32-bit address bus and cache memory of 1024 words. If a direct mapped cache with one-word block size is used to implement this cache then it has memory word (cache memory word length) of size —- i. 32 bits ii. 20 bits iii. 42 bits iv. 21 bits v. 43 bits (e) A two-way set-associate mapping cache —– hold two memory locations with same set fields. i. can ii. cannot 1. Multiple Choice Questions (MCQs), [15 points, 3 points/MCQ] (a) An ALU (Arithmetic Logic Unit) is a —— . i. combinational logic circuit ii. sequential logic circuit iii. none of the above (b) A computer system has a common bus system (constructed using MUXs) for 64 registers of 4-bit each. Each MUX has — select inputs and a total of —- MUX are needed. i. 8, 4 ii. 4, 8 iii. 8, 8 iv. 6, 4 (c) A two-way set associate cache always has a lower miss rate then a direct mapped cache with same block size and total capacity. i. YES – Justification: —- ii. NO – Justification: —- (d) Consider a MIPS processor with 32-bit address bus and cache memory of 1024 words. If a direct mapped cache with one-word block size is used to implement this cache then it has memory word (cache memory word length) of size —- i. 32 bits ii. 20 bits iii. 42 bits iv. 21 bits v. 43 bits (e) A two-way set-associate mapping cache —– hold two memory locations with same set fields. i. can ii. cannot

Explanation / Answer

Following are the answers for questions sharaed.

a) combinational logic circuit(i)
b) 6,4 (iv)
c) Yes (i)
Because larger sets and higher associativity leads to fewer cache conflicts and
lower miss rates, but they also increase the hardware cost.
d) (i)
e) cannot (ii)

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