1. A ________ implementation of a processor architecture is one in which common
ID: 3829325 • Letter: 1
Question
1. A ________ implementation of a processor architecture is one in which common instructions can be initiated simultaneously and executed independently.
2. The term ________ refers to a machine that is designed to improve the performance of the execution of scalar instructions.
3. ________ exploits the fact that many pipeline stages perform tasks that require less than half a clock cycle.
4. The term _________ parallelism refers to the degree to which, on average, the instructions of a program can be executed in parallel.
5. A _________ is a competition of two or more instructions for the same resource at the same time.
6. _________ is a measure of the ability of the processor to take advantage of instruction-level parallelism.
7. Committing or _________ the instruction is when instructions are conceptually put back into sequential order and their results are recorded.
8. In the operation of the Intel Core each instruction is translated into one or more fixed-length RISC instructions known as _________.
9. The ________ protects critical data used by the operating systemfrom user applications, separating processing tasks by disallowing accessto each other’s data, disabling access to memory regions, allowing memoryregions to be defined as read-only, and detecting unexpected memory accessesthat could potentially break the system.
10. The _________ predicts the instruction stream, fetches instructions from the L1 instruction cache, and places the fetched instructions into a buffer for consumption by the decode pipeline.
11. Instruction-level parallelism is also determined by __________, which is the time until the result of an instruction is available for use as an operand in a subsequent instruction.
12. Superscalar instruction issue policies are grouped into the following categories: in-order issue with in-order completion, out-of-order issue with out-of-order completion, and ____________.
13. With ____________ any number of instructions may be in the execution stage at any one time, up to the maximum degree of machine parallelism across all functional units.
14. The ________ is a buffer used to decouple the decode and execute stages of the pipeline to allow out-of-order issue.
15. An alternative to _________ is a scoreboarding.
Explanation / Answer
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1. A Supersca;ar implementation of a processor architecture is one in which common instructions can be initiated simultaneously and executed independently.
2. The term superscalar refers to a machine that is designed to improve the performance of the execution of scalar instructions.
3. SuperPipelining exploits the fact that many pipeline stages perform tasks that require less than half a clock cycle.
4. The term instruction-level parallelism refers to the degree to which, on average, the instructions of a program can be executed in parallel.
5. A resource conflict is a competition of two or more instructions for the same resource at the same time.
6. Machine parallelismis a measure of the ability of the processor to take advantage of instruction-level parallelism.
7. Committing or retiring the instruction is when instructions are conceptually put back into sequential order and their results are recorded.
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