In the multiple-issue design of Problem 1,you may have recognized some subtle is

Question

In the multiple-issue design of Problem 1,you may have recognized some subtle issues. Even though the two execution pipelines have the exact same instruction repertoire, they are neither identical nor interchangeable, because there is an implicit ordering between them that must reflect the ordering of the instructions in the original program. What this means is, if instruction N+ 1 begins execution in Pipe 1 at the same time that the instruction N begins in Pipe 0, and N +1 happens to require a shorter execution latency than N, then N 1 will complete before N (even though the program ordering would have implied otherwise). Recite at least two reasons why that could be hazardous and will require special considerations in the micro-architecture. Give at least 1 example of two instructions from the code using information in Table 1 that demonstrated this hazard.

Explanation / Answer

Ans::

-->.1. If an interrupt occurs betweeen "N" & "N + 1"., then ' N + 1 ' mustn't have been

'allowed' to write its results to any 'permanent_architecturl_state'.--> Alternatively.,

it could be 'permissible' to delay the 'interrupt' until '' N + 1 '' completes.

-->.2. If 'N' and 'N + 1' happen to 'target' the same_registr or architectural_state (--memory)., then allowing 'N' to over_write what ' N + 1 ' wrote wouldd be 'wrong'.

-->.3. 'N' might be long '' floating--point'' op that eventually 'traps'. "N + 1"can't be

allowed to change "arch_state" in case ''N'' is to be ''retried''.

-->"Long--latency" ops are at the 'highest-risk' of being 'passed' by a subsequent ''op''.

-->Example:: The "DIVD--instr" will complete 'long after' the "" LD F4,0(Ry) "" . // thank you //

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