/******************************************************************** This is my
ID: 3834346 • Letter: #
Question
/********************************************************************
This is my code implimenting a washer machine in Verilog (code C)
This project is suppose to take a payment in increments of 25 cents and
be able to do a basic (50cents), normal (75cents), and heavy (1dollar) wash loads
while the lid is closed. everything seems to work except for one thing.
The payment case or my count isnt working. It doesn not increment and i dont know why.
please help. I NEED HELP ONLY WITH THE BUG IN MY PAYMENT CASE OR COUNT.
*****************************************************************************************************/
module VerilogFinal_Lopez(lid,clk, payment, selection , led ,ssdL, ssdR);
input clk;
input payment;
input [2:0] selection;
input lid;
output reg [7:0] led;
output reg [6:0] ssdL, ssdR;
reg [6:0] count, next_state;
localparam c00 = 0;
localparam c25 = 25;
localparam c50 = 50;
localparam c75 = 75;
localparam c10 = 100;
localparam l0 =0;
localparam l1 = 1;
localparam l2 = 2;
localparam l3 = 3;
localparam l4 = 4;
localparam id = 0;
localparam basicL = 3'b001;
localparam normalL = 3'b010;
localparam heavyL = 3'b100;
localparam quarter = 2'b01;
localparam reset = 2'b10;
always@(posedge clk)
begin
count = next_state;
end
always@(selection, payment, count, lid)
begin
case(lid)
id: begin
ssdL = 7'b1111111; //8
ssdR = 7'b1011111; //6
end
endcase
case(payment)
quarter: next_state = count + c25;
reset: next_state = c00;
default: next_state = count;
endcase
// case(led)
// l0:
case(count)
c00:
begin
ssdL = 7'b1111110; //0
ssdR = 7'b1111110; //0
end
c25:
begin
ssdL = 7'b1101101; //2
ssdR = 7'b1011011; //5
end
c50:
begin
ssdL = 7'b1011011; //5
ssdR = 7'b1111110; //0
led = 4'b0001;
end
c75:
begin
ssdL = 7'b1110000; //7
ssdR = 7'b1011011; //5
end
c10:
begin
ssdL = 7'b0110000; //1
ssdR = 7'b1111110; //0
end
default:
begin
ssdL = 7'b1111110; //0
ssdR = 7'b1111110; //0
end
endcase
case (selection)
basicL:
begin
if (count >= c50 && lid == 1)
begin
ssdL = 7'b0011111; //b
ssdR = 7'b1001110; //C
end
else
begin
ssdL = 7'b1001110; // C
ssdR = 7'b0000101; //low funds or lid open "r"
end
end
normalL:
begin
if(count >= c75 && lid == 1)
begin
ssdL = 7'b0010101; // n
ssdR = 7'b1111110; //0
end
else
begin
ssdL = 7'b1001110; // C
ssdR = 7'b0000101; //low funds or lid open "r"
end
end
heavyL:
begin
if(count >= c10 && lid == 1)
begin
ssdL = 7'b0110111; //H
ssdR = 7'b0111011; //y
end
else
begin
ssdL = 7'b1001110; // C
ssdR = 7'b0000101; //low funds or lid open "r"
end
end
endcase
end
endmodule
Explanation / Answer
module VerilogFinal_Lopez(lid,clk, payment, selection , led ,ssdL, ssdR);
input clk;
input payment;
input [2:0] selection;
input lid;
output reg [7:0] led;
output reg [6:0] ssdL, ssdR;
reg [6:0] count, next_state;
localparam c00 = 0;
localparam c25 = 25;
localparam c50 = 50;
localparam c75 = 75;
localparam c10 = 100;
localparam l0 =0;
localparam l1 = 1;
localparam l2 = 2;
localparam l3 = 3;
localparam l4 = 4;
localparam id = 0;
localparam basicL = 3'b001;
localparam normalL = 3'b010;
localparam heavyL = 3'b100;
localparam quarter = 2'b01;
localparam reset = 2'b10;
always@(posedge clk)
begin
count = next_state;
end
always@(selection, payment, count, lid)
begin
case(lid)
id: begin
ssdL = 7'b1111111;
ssdR = 7'b1011111;
end
endcase
case(payment)
quarter: next_state = count + c25;
reset: next_state = c00;
default: next_state = count;
endcase
// case(led)
// l0:
case(count)
c00:
begin
ssdL = 7'b1111110; //0
ssdR = 7'b1111110; //0
end
c25:
begin
ssdL = 7'b1101101;
ssdR = 7'b1011011;
end
c50:
begin
ssdL = 7'b1011011; //5
ssdR = 7'b1111110; //0
led = 4'b0001;
end
c75:
begin
ssdL = 7'b1110000;
ssdR = 7'b1011011; //5
end
c10:
begin
ssdL = 7'b0110000; //1
ssdR = 7'b1111110;
end
default:
begin
ssdL = 7'b1111110;
ssdR = 7'b1111110;
end
endcase
case (selection)
basicL:
begin
if (count >= c50 && lid == 1)
begin
ssdL = 7'b0011111;
ssdR = 7'b1001110;
end
else
begin
ssdL = 7'b1001110; // C
ssdR = 7'b0000101; //low funds or lid open "r"
end
end
normalL:
begin
if(count >= c75 && lid == 1)
begin
ssdL = 7'b0010101;
ssdR = 7'b1111110;
end
else
begin
ssdL = 7'b1001110; // C
ssdR = 7'b0000101;
end
end
heavyL:
begin
if(count >= c10 && lid == 1)
begin
ssdL = 7'b0110111; //H
ssdR = 7'b0111011; //y
end
else
begin
ssdL = 7'b1001110; // C
ssdR = 7'b0000101; //low funds or lid open "r"
end
end
endcase
end
endmodule
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