1. [1] What is the cache line size? 2. [1] How many entries does the cache have?

Question

1. [1] What is the cache line size? 2. [1] How many entries does the cache have? 3. [5] Starting from power on, the following byte addressed cache references are recorded. 4,16,132,5,4,6,132, 232. Compute the hit ratio for this sequence of addresses. Give the final state of the cache as a record of <index, tag, data>

B. [1] Calculate AMAT for a cache if hit time is 0.62ns, miss rate is 11.4% and miss penalty is 70ns. C. [2] Calculate the page table size if virtual address size is 64 bits, page size is 16 KB and page table entry size is 8 bytes

A. For a direct mapped cache design with 32-bit address, the following bits of the address are used to access the cache Offset Tag Index 31-10 9-4 3-0

Explanation / Answer

1).[1] Since Offset field is 4 bits, then cache line/block size is 16 bytes; i.e. 4 words

[2].Since Index field is 6 bits, then number of entries/blocks is 64 blocks

[3] Hit ratio = number of hits/total number of accesses

[4].Final state: . (The index and tag are shown in binary)

<000000, 0001, mem[1024]>

<000001, 0011, mem[3088]>

<001011, 0000, mem[176]>

<001000, 0010, mem[2176]>

<001110, 0000, mem[224]>

<001010, 0000, mem[160]>

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