The following figure describes the architecture of a computer that implements ad

Question

The following figure describes the architecture of a computer that implements address translation
through paging. The page table is stored as two level hierarchical structure.

1. Compute the values of x, y and z in the picture

2. Compute the size in bits of the first level page table

3. Compute the size of a second level page table (3 Pts)

1 Byte Virtual Memory VA x+8 x+5 Address Address ndex to 2nd level PT ndex to 1st level PT First level page table Frame, Size 16 Kilobits Physical Memory 1 Byte Address 0 To second level page tables Address 232-1

Explanation / Answer

We can see that frame Size is : 16KiloBytes = 24 * 210 = 214

1. x = 14

2. Now we can see that physical memory is 32 bits , So that means

32 - 14 = 18 bits

So that means y = 18 bits

3. Since x = 14 bits ,

0--14---19---22 : That means Z = 23 bits from 0 to 22

Z = 23


Size in bits of first level page table = x +5 to x+8
0--14--19---22 , That means 3 bits to mqp each page:

23x1 byte per entry = 25


Size in bits of 2nd level page table = x . to x+5
0--14--19 , That means 5 bits to mp each page:

25x1 byte per entry = 28

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