Academic Integrity: tutoring, explanations, and feedback — we don’t complete graded work or submit on a student’s behalf.

Consider the following code segment executes on a 5-stage MIPS pipeline: Loop: l

ID: 3838896 • Letter: C

Question

Consider the following code segment executes on a 5-stage MIPS pipeline:
Loop: lw $3, 0($zero)
lw $1, 0($3)
addi $1, $1, #1
sub $4, $3, $2
sw $1, 0($3)
bne $4, $zero, Loop

(a) Show a pipeline execution diagram without any forwarding or data hazard detection hardware.Assume a register read and write in the same cycle, (i.e., register write occurs in the first half of the cycle and register read occurs on the second half of the cycle). Also, assume the outcome of the branch and the branch target address is known and forwarded in the MEM stage. Insert NOPs for the correct execution of the code.
(b) Show a pipeline execution diagram with data forwarding and hazard detection hardware. Assume the outcome of the branch and the branch target address is known and forwarded in the MEM stage.
(c) Show a pipeline execution diagram with data forwarding and hazard detection hardware. Assume the outcome of the branch and the branch target address is known and forwarded in the ID stage.

Explanation / Answer

You may work in sets for this task. On the off chance that you work with an accomplice, ensure just a single of you makes an accommodation an answer and that the record records names and PIDs for both of you as depicted in the task underneath.
Set up your responses to the accompanying inquiries in a plain content record. Present your document to the Curator framework by the posted due date for this task. No late entries will be acknowledged.
You will present your responses to the Curator System (www.cs.vt.edu/guardian) under the heading MIPS04.
For inquiries 1 through 3, allude to the pipeline outline with sending, demonstrated as follows, which underpins execution of the accompanying MIPS directions: include, sub, and, or, slt, and sw, and lw inasmuch as no slows down are expected to determine stack utilize perils.
Keep in mind: this pipeline configuration does exclude (stack utilize) danger discovery equipment, so it can forward operands however it can't acquaint slows down with manage circumstances that sending alone won't deal with.

Hire Me For All Your Tutoring Needs
Integrity-first tutoring: clear explanations, guidance, and feedback.
Drop an Email at
drjack9650@gmail.com
Chat Now And Get Quote