For a direct-mapped cache design with a 32-bit address, the following bits of th

Question

For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag Index Offset 31 - 12 11 - 7 6 - 0 1.1) What is the cache block size (in words)? 1.2) How many entries does the cache have? 1.3) What is the ratio of the total number of bits required for such a cache implementation (i.e., data, tag, valid bit) over the number of bits needed for data storage? [Hint: examples in the book around Figure 5.10.] 1.4) How many blocks are replaced with the following accesses? [Hint: fill in the following table. “Block ID in cache” is “Block Address” mod “# of entries in cache”.] Starting from an empty cache, the following byte-addressed cache references are recorded. 1 348 756 9870 7980 364 4360 614 4740 3000 1440 2280 Byte Address 1 348 756 9870 7980 364 4360 614 4740 3000 1440 2280 Block Address 0 77 34 Block ID in cache 0 13 2 Hit/Miss M M H Replace? (Y/N) N N Y 1.5) What is the hit ratio? 1 1.6) List the final state of the cache similar to Figure 5.9f. However, show only the final state (no intermediate steps) and only the valid entries (no need to show empty or not valid entries).

Explanation / Answer

A direct-mapped cache design with a 32-bit address Tag Index Offset 31 - 12 11 - 7 6 - 0
1) Cache cache block size = 2offset bits= 27 bits = 25 words
2) Entries the cache have = 2 index bits= 25
3) (Tag bits + valid bit + data bits)/data bits = (20+1+16*8)16*8= 1.16

5) Hit Ratio= 1/3=.33

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