Closed book/notes test (Exception: the MIPS reference sheet and one page single

Question

Closed book/notes test (Exception: the MIPS reference sheet and one page single side 8" times 11" notes.) May use scientific or graphing calculator, but no other electronic devices (cell phone etc.) allowed, even to be used as a calculator. No questions will be answered during the exam or immediately afterwards (exception: correction of typos.) Answer each question as best you can. Partial credit will be awarded for reasonable efforts. If a question contains an ambiguity or a misprint, then say so in your answer, providing the answer to a reasonable interpretation of the question; give your assumptions. Answer the problems on the blank spaces provided for each problem. If additional space needed, clearly indicate where your answer continues. If you finish early, bring your exam to the front; then leave quietly. Multiple Choice (choose one answer only) or True/False. For cache performance improvement, using multi-level cache (L1 - L2 etc.) will (a) reduce the miss penalty. (b) increase the miss rate. (c) reduce cache storage overhead. (d) None of above. If a processor has a clock rate of 2 GHz, the clock cycle time is. (a) 2 nanoseconds (b) 500 picoseconds (c) 200 microseconds (d) 500 nanoseconds (e) None of above DRAM is non-volatile semiconductor memory. T or F RAID 0 provides availability but doesn't provide reliability. T or F In RAID 5 there are n data disks and 1 dedicated check disk. T or F

Explanation / Answer

1. a) reduce the miss penalty3

2. d) none of the above

using the formula clock cycle=1/clock rate

1/2000000000=50 nanoseconds

3. False

As it looses its data as soon as the power is turned OFF.

4. True

As RAID 0 provides availability by adding redundant disks

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