a) A 5-Stage pipeline is composed of the following stages Instruction Fetch (IF)

Question

a) A 5-Stage pipeline is composed of the following stages Instruction Fetch (IF), Decode (DE), Execute (EX), Memory Access (ME) and Register Write-back (WB). Assume the pipeline does not have a branch prediction unit, does not have superscalar support and does not support out of order execution. Assume that all memory accesses are in the L1 cache and therefore do not introduce any stalls. Show a pipeline diagram that shows the execution of each stage for the assembly code below. Also specify why each pipeline Stall is introduced. add %rax, (%rbx) subq %rcx, %rax movq $0, %rdx movq $1, %rdx xorq %rsi, (%rbx) movq %rsi, %r10 movq %r10, %r11

Explanation / Answer

Explanations for NOP (stalls) are :-

1)subq %rcx,%rax - dependency of value in %rax in the previous instruction due to which the pipeline gets stalled untill the WB is not done

2)movq %r10,%r11- dependency of value in %r10 from the previous instruction due to which pipeline gets stalled

Instructions:- 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 addq %rax,($rbx) IF DE EX MEM WB subq %rcx,%rax NOP NOP IF DE EX MEM WB movq $0,%rdx IF DE EX MEM WB movq $1,%rdx IF DE EX MEM WB xorq %rsi,(%rbx) IF DE EX MEM WB movq %rsi,%r10   IF DE EX MEM WB movq %r10,%r11 NOP NOP IF DE EX MEM WB

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