I\'ve the answer. Please explain and show your work. 1. A non-pipelined processo

Question

I've the answer. Please explain and show your work. 1. A non-pipelined processor takes 5 ns to execute instructions in its ISA. What is the maximum clock frequency in gigahertz at which you can use for this processor based on this information. Answer is 0.2

2. A prcoessor pipelined is implemented that consists of 5 perfectly balanced pipelines stages. The implementation introduces an additional 25% per stage clock penealty over an ideal cycle time. What will be the performance ratio of a processor with this pipeline to that of a processor without any pipeline register delay. Assume no hazards . Answer is 0.8

3. A pipeline takes some time to fill and some time to empty. A 10-stage non-ideal pipelined processor runs at 1GHz. What is the speedup of the pipelined machine for a program consisting of only 21 instructions.Assume no hazards in the program. Answer is 9

Explanation / Answer

1.

      Given Time taken for a non-pipelined processor is = 5 ns.

       We know clock frequency = 1 / Time period

                                             = 1 / (5 * 10-9)

                                                            = (1 / 5 ) * 109

                                                            = 0.2 GHz

       Hence clock frequency is = 0.2 GHz.

2.

      We know that the time taken for a k stage pipelined processor for executing

      n instructions is = (k+n-1) * clock penealty.

      Consider the clock penealty for this pipeline is = x.

      Hence the time taken will be = (k+n-1) * x.

      Now if we increase the clock penealty to 25% then clock penealty = x + x * 25/100 = 5x/4.

      Hence performance ratio will be = x / 5x/4 = 4/5 = 0.8.

3.

speedup of the pipelined machine is = Time on non pipelined processor / Time on pipelined processor

   Here clock period is = 1 / frequency = 1 / 109 = 1 ns(time taken for one stage).

   Hence Time on non pipelined processor for one instruction is = 10 * 1ns = 10ns (10 stages for instruction).

Time on non pipelined processor for 21 instructions is = 21 * 10 ns = 210 ns.

   Time taken for pipelined processor is = (k+n-1) * clock period = (10+21-1) * 1ns = 30 ns

   Hence speedup is = 210 / 30 = 7.

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