The 8086\'s 6-byte long prefetch queue was a structure that aided processor perf

Question

The 8086's 6-byte long prefetch queue was a structure that aided processor performance as long as the instruction execution sequence was implemented (with for-next loops/circularly/randomly/linearly/using many branches circle one). Externally, the 8086 had a ____ address/data bus, which meant that the address signals and the data signals shared the same pins on the chip. This meant that the address had to be latched into external circuitry (before/after circle one) the data was on the bus. To accomplished the latching, the 8086 (and 8088) had an additional pin, called ____ to allow the external circuitry to latch in the address. Upon reset, the CS register is loaded with ____ and the instruction pointer register is loaded with ____, for a real-mode physical address of _____ hex.

Explanation / Answer

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The 8086's 6 byte long perfetch queue was a structure that aided processor performance as long as the instruction exection sequence was implemented linearly. Extremely the 8086 had a databus,which meant that the address signals and te data signals shared the same pins on chip. This meant that the address had to be latched into external circutary before the data was on the bus. To accomplish latching the 8086 had an additional pin called ALE to allow an external circuitary to latch in the address. Upon rest the CS register is loaded with data value and the instruction pointer register is loaded with AL for real mode physical address of hex

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