Assume a processor with 5 stages like the one discussed in class and the text. A

Question

Assume a processor with 5 stages like the one discussed in class and the text. Answer the following questions assuming the 5 stages have the following latencies: What is the single cycle time for this processor? _____ If the 5 stages are pipelined what is the cycle time for this processor? _____ How long will a single instruction take from start to finish in the 5 stage pipeline? _____ If the company develops faster memories and reduces the IM latency to 175 ps and the Data Memory(DM) latency to 180 ps what is the speedup for the updated processor? Assume all other latencies remain the same. Calculate the speedup for both the single cycle and the pipelined versions. Single cycle speedup _____ Pipelined processor speedup _____

Explanation / Answer

Answer 1a: Single cycle time= 240 + 200 + 100 + 250 + 100 = 890 ps

Answer 1b: As we have 5 stages are Pipelined that reduces the cycle time to the length of the longest stage.

In this case cycle time= 250 ps

Answer 1c: Single instruction time from start to finish in 5 stage pipeline = 5* 250 = 1250 ps

Answer 2a: Single cycle speedup = 175 + 200 + 100 + 180 + 100 = 755 ps

Speed up = Old execution time/New execution time = 890/755 = 1.179x

Answer 2b: Pipelinedcycle speedup = 200 ps

Speed up = Old execution time/New execution time = 250/ 200 = 1.25x

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