Assume the following computer system. The I/O device currently holds 10MB of dat

Question

Assume the following computer system. The I/O device currently holds 10MB of data to be transferred to the main memory. Each data transfer between the I/O device and the I/O controller takes 100 mu s. Each data transfer using the internal bus takes l00 mu s The I/O device and the I/O controller are connected by 16-parallel wires (16 bits can be transferred in one shot). The I/O controller, the processor and the memory are connected by 16-parallel wires (16 bits can be transferred in one shot). Each context switching takes the processor 50 mu_s. Each interrupt transfers 16 bits while DMA can transfer any number of bits (but a multiple of 16 bits) in one DMA transfer session. Ignore any other overhead How long will it take to complete data transfer using interrupt and DMA?

Explanation / Answer

Direct Memory Access (DMA)

Interrupt Handling

Here we describe interrupt handling in a scenario where the hardware does not support identifying the device that initiated the interrupt. In such cases, the possible interrupting devices need to be polled in software.

Interrupt Acknowledge Cycle

Here we describe interrupt handling in a scenario where the hardware does support identifying the device that initiated the interrupt. In such cases, the exact source of the interrupt can be identified at hardware level.

Synchronization Requirements for DMA and Interrupts

Many times software designers have to work with data structures that are shared with interrupts or DMA devices. This requires performing atomic updates to the shared critical regions.

Synchronization With Interrupts

When a data structure is shared with an ISR, disabling the interrupt to execute the critical region updates is a good technique. Keep in mind that disabling of interrupts should be restricted to only the code that updates the critical region. Keeping the interrupts disabled for a long time will increase the interrupt latency.

Another option is to make use of the fact that interrupts are processed at instruction boundaries. A single instruction that performs read as well as write could be used to perform an atomic transaction. For example, if your processor supports direct memory increment, you could increment a shared semaphore without disabling interrupts.

Synchronization With DMA

Sharing data structures with a DMA device is tricky. The processor can initiate a DMA operation at a bus cycle boundary. This means that a new DMA operation can be started in the middle of an instruction execution (Keep in mind that an instruction execution involves multiple bus cycles).

The best mechanism to perform critical region updates is to use the read-modify-write bus cycle. With this instruction, atomic updates can be made to critical regions as the read and write are glued together in a special bus cycle.

Another option is to disable DMA operation. Extreme caution should be used when employing these techniques.

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