Using the same entity created below, create a logic equation or \"dataflow\" mod

Question

Using the same entity created below, create a logic equation or "dataflow" model for the

sequencer Your test bench should be identical to the test

bench created in Part 3.

library ieee;
use ieee.std_logic_1164.all;
entity detector is
port (rst,clk,x:in std_logic;
z:out std_logic);
end detector;

architecture behavior of detector is
type STATE_TYPE is (S_0,S_1,S_2,S_3,S_4,S_5);
signal state, next_state : STATE_TYPE;
  
begin
  
process(rst,clk)
begin
if (rst='1') then
state<=S_0;
elsif (clk'event and clk='1') then
state<=next_state;
end if;
end process;
  
process (state,x)
begin

case state is
when S_0 =>
if (x='0') then
next_state<=S_1;
z<='0';
else
next_state<=S_0;
z<='0';
end if;
  
when S_1 =>
if (x='0') then
next_state<=S_2;
z<='0';
else
next_state<=S_0;
z<='0';
end if;
  
when S_2 =>
if (x='0') then
next_state<=S_3;
z<='0';
else
next_state<=S_0;
z<='0';
end if;
  
when S_3 =>
if (x='0') then
next_state<=S_3;
z<='0';
else
next_state<=S_4;
z<='0';
end if;
  
when S_4 =>
if (x='0') then
next_state<=S_1;
z<='0';
else
next_state<=S_5;
z<='0';
end if;
  
when S_5 =>
if (x='0') then
next_state<=S_1;
z<='1';
else
next_state<=S_0;
z<='0';
end if;

end case;   
end process;
  
end behavior;

Explanation / Answer

sequencer Your test bench should be identical to the test
bench created in Part 3.
library ieee;
use ieee.std_logic_1164.all;
entity detector is
port (rst,clk,x:in std_logic;
z:out std_logic);
end detector;
architecture behavior of detector is
type STATE_TYPE is (S_0,S_1,S_2,S_3,S_4,S_5);
signal state, next_state : STATE_TYPE;
  
begin
  
process(rst,clk)
begin
if (rst='1') then
state<=S_0;
elsif (clk'event and clk='1') then
state<=next_state;
end if;
end process;
  
process (state,x)
begin
case state is
when S_0 =>
if (x='0') then
next_state<=S_1;
z<='0';
else
next_state<=S_0;
z<='0';
end if;
  
when S_1 =>
if (x='0') then
next_state<=S_2;
z<='0';
else
next_state<=S_0;
z<='0';
end if;
  
when S_2 =>
if (x='0') then
next_state<=S_3;
z<='0';
else
next_state<=S_0;
z<='0';
end if;
  
when S_3 =>
if (x='0') then
next_state<=S_3;
z<='0';
else
next_state<=S_4;
z<='0';
end if;
  
when S_4 =>
if (x='0') then
next_state<=S_1;
z<='0';
else
next_state<=S_5;
z<='0';
end if;
  
when S_5 =>
if (x='0') then
next_state<=S_1;
z<='1';
else
next_state<=S_0;
z<='0';
end if;
end case;
end process;

end behavior;

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