2. A generic computer has a two level cache, suppose the CPU makes a series of 4
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Question
2. A generic computer has a two level cache, suppose the CPU makes a series of 4000 address requests. The L1 cache, L2 cache, and main memory response times are 25ns, 50ns, and 200ns, respectively.
a. The L1 cache satisfies 3690 of the requests made by the CPU. What is the L1 cache hit rate and miss rate?
b. The L2 cache satisfies 295 of the requests made by the CPU. How many requests are actually made to the L2 cache for addresses? What is the L2 cache hit rate and miss rate?
c. Calculate the average access time.
Consider the given memory map, the addresses assume a 14 bit long bit field. 0x3fff ROM 0x2200 0x0aff 0x0100 RAM 0x0000 a. Calculate the number of bytes in each region where memory devices appear. For sizes 1024 or larger give the value units of lk, otherwise give the value in bytes b. Indicate whether or not each of the following addresses correspond to a memory device, if so also indicate which device: $002b, $1f02, $0900, $2C00Explanation / Answer
Q1.
A) The given addresses are in hexadecimal .
Converting RAM higher address i.e. 0x0aff (hexa) to binary: 0000101011111111
Converting RAM lower address i.e. 0x0100 (hexa) to binary : 0000000100000000
Subtracting both the address : 0000100111111111
Converting the result to decimal = 2559
The total address =2559+1=2560
Since, each adddress is of 14 bits .
HENCE, total memory aquired by RAM = 2560*14 bits= 35840 bits =4480 Bytes = 4KB and 384 Bytes
Converting ROM higher address i.e. 0x3fff (hexa) to binary : 0111111111111111
Converting ROM lower address i.e. 0x2200 (hexa) to binary : 0010001000000000
Subtracting both the address : 0001110111111111
Converting the result to decimal = 7679
The total address =7679+1=7680
Since, each adddress is of 14 bits .
HENCE, total memory aquired by ROM = 7680*14 bits= 107520 bits =13440 Bytes = 13KB and 128 Bytes
B) Converting RAM higher address i.e. 0x0aff to decimal : 2815
Converting RAM lower address i.e. 0x0100 to decimal : 256
Converting ROM higher address i.e. 0x3fff to decimal : 16383
Converting ROM lower address i.e. 0x2200 to decimal : 8704
Converting Given address 1 i.e. 002b (hex) to decimal : 43
Given address 2 i.e. 0x1f02 to decimal : 7938
address 3 i.e. 0x0900 to decimal : 2304
addres 4 i.e. 0x2c00 to decimal :11264
Since address 1 and address 2 neither come in range 256-2815 (RAM) nor in range 8704-16383 (ROM)
Thus, they don't correspond to memory device
Since address 3 comes in range 256-2815 (RAM).
Thus, it corresponds to memory device RAM
Since address 4 comes in range 8704-16383 (ROM).
Thus, it corresponds to memory device ROM
Q2.
A) L1 cache hits= 3690
Total address request= 4000
L1 Cache Hit Rate(H1)= (No. of Hit/ Total request)
=(3690/4000)
=0.9225
L1 Cache Miss Rate(1-H1)= 1- L1 Cache Hit Rate
= 0.0775
B) L2 cache hits= 295
Total address request made to L2 cache= 4000-3690=310
L2 Cache Hit Rate(H2)= (No. of Hit/ Total request)
=(295/310)
=0.95 (approx)
L2 Cache Miss Rate(1-H2)= 1- L2 Cache Hit Rate
= 0.05 (approx)
C) Average access time = [H1*T1]+[(1-H1)*H2*T2]+[(1-H1)(1-H2)*Hm*Tm]
T1=25ns
T2=50ns
Tm=200ns
Average access time = [0.9225*25]+[0.0775*0.95*50]+[0.0775*0.05*1*200] {Hm=1}
= 23.0625 + 3.68125 + 0.775
=27.51875 ns
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