Consider a non-pipelined, non-parallel, sequential machine. The CPU executes eac

Question

Consider a non-pipelined, non-parallel, sequential machine. The CPU executes each machine instruction in a series of small steps as indicated in the list of Section 2.1.2 (page 58) of the textbook. Explain precisely what needs to be done at hardware level in Step (6) If the machine instruction currently being executed is an unconditional "branch" instruction in the form: JUMP 8000. State precisely which of the four registers located in the CPU and mentioned in the previous question are consulted and/or modified and how. What is the purpose of Step (2) in the list of Section 2.1.2? What would happen if this step is completely omitted? Is it possible to move Step (2) and place it after Step (6) but before Step (7) Consider the hypothetical machine discussed in class. Write machine instruction for doubling the contents of register 5 Write machine instruction for rotating the bit pattern in register 8, five bits to the left Provide English language description of the machine instruction: BBBB Provide English language description of the machine instruction: 9123 Consider the hypothetical machine discussed in class. Write machine instruction for doubling the contents of register 5 Write machine instruction for rotating the bit pattern in register 8, five bits to the left Provide English language description of the machine instruction: BBBB Provide English language description of the machine instruction: 9123 Consider the hypothetical machine discussed in class. Suppose the variable w occupies the memory cell, whose address in hex is 80.

Explanation / Answer

Hi, Not sure exactly which question to answer and other questions lack details in image so providing answer for question-5

instruction for doubling the contents of register: suppose a register is $s5

add $s4, $s4, $s4

machine instruction for rotating bits, 5 bits to left:

ssl $s7, $s7, 5

BBBB

it is used in term of masking the value in branching mechanism.

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