3. Suppose the logic blocks in a processor have the following latencies.. Data a

Question

3. Suppose the logic blocks in a processor have the following latencies.. Data access Register write 350ps 150ps 175ps 500ps 200ps a) In a single cycle, non-pipelined processor, what is the minimum time between instructions for an application executing only R-type instructions? b) In a single cycle, non-pipelined processor, what is the minimum time between instructions for an application executing R, I, and J-type instructions? c) If the logic blocks above are each implemented as individual pipeline stages, what would be the minimum time between instructions for this pipelined CPU if hazards are ignored?

Explanation / Answer

In no pipelining, the cycle time must allow an instruction to go through all stages in one cycle. The latency is the same as cycle time since it takes the instruction one cycle to go from the beginning of fetch to the end of writeback.

for R type instruction: 400ps+150+200+520+220=1420ps

for I type instruction: for immediate type inst there is no need of register write because it wil update in memory only like store inst

therefore:400=150+200+520=1270ps

for j type inst:In jump instruction ,it wil go to instruction fetch to inst decode only so

400+150=550ps

In Pipelining reduces the cycle time to the length of the longest stage plus the register

delay if present

therefore:520ps is the ans

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