Multitasking and Context Switching; Pipelining Assume a 5-stage pipelined proces

Question

Multitasking and Context Switching; Pipelining

Assume a 5-stage pipelined processor using the standard 5-stages (IF, ID, EX, MEM, WB) that uses no forwarding or stalling circuitry. Rather, you will use the compiler to add no-ops to the code to ensure correct execution.

Note: You can assume that if the processor reads and writes to the same register in a given cycle, the value read out will be the new value that is written in that cycle.

Write your own short program that re-writes the code below including the no-ops that are needed to protect against hazard conditions.

Explanation / Answer

Answer is as follows :

Pipeline diagram with given scenario :

Hazard Conditions ( with no forwarding) :

add $3, $2, $3 // instruction 1

lw $4, 100($3) // instruction 2

sub $7, $6, $2 // instruction 3

xor $6, $4, $3 // instruction 4

No other hazards are possible for given data. The RAW hazard is occur, as we perfrom the calculations on $3 to obtain some memory locations. so first we have to read it. So RAW is present in this

So re-write code with no-ops :

add $3, $2, $3

NOP

lw $4, 100($3)

sub $7, $6, $2

NOP

xor $6, $4, $3

if there is any query please ask in comments..

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 add $3, $2, $3 IF ID EX MEM WB lw $4, 100($3) IF * ID EX MEM WB sub $7, $6, $2 IF ID EX MEM WB xor $6, $4, $3 IF * ID EX MEM WB

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