5. Consider the following simple program executed on a pipelined MIPS CPU addi $

Question

5. Consider the following simple program executed on a pipelined MIPS CPU addi $s0, Szero, 3 LOOPwS add $t1, St0, $t2 add St3, Stl, St4 addi Ss0, $s0,-1 bne $s0, $zero, LOOP addi Ssl, Szero, Szero a) How many cycles will be required for the program to fully execute on a 5 stage pipeline with forwarding and perfect branch prediction? b) How many cycles will be required for the program to fully execute on a 5 stage pipeline that has no forwarding or branch prediction, but automatically inserts a minimal number of stalls?

Explanation / Answer

Answer is as follows :

For the given scenario, first we have to make pipeline diagrams,

So

a) Pipeline with forwarding and perfect branch Prediction

So from above 5-stage pipeline diagram we get that it takes 12 cycles to execute.

* is indicated as stall here. lw instruciton takes one more cycle to load a word, so next instruciton have to wait due to stall occur.

b) Pipeline diagram without forwarding :

So from above we get there are 16 cycles due to without forwarding.

if there is any query please ask in comments...

1 2 3 4 5 6 7 8 9 10 11 12 13 14 instruction 1 IF ID EX MEM WB instruction 2 IF ID EX MEM WB instruction 3 IF * ID EX MEM WB instruction 4 IF ID EX MEM WB instruction 5 IF ID EX MEM WB instruction 6 IF ID EX MEM WB instruction 7 IF ID EX MEM WB

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