The following given Verilog modules are for the next two questions. /D flip-flap

Question

The following given Verilog modules are for the next two questions. /D flip-flap with asynchronaus reset module DFF (output reg 0. input D, Clk, RstH always @(posedge Clk, posedge Rst) module count4 output [3: 0. input Clk. input Rst) wire a, b, c, d assign a -0I11: assign b 012]: assign c-013 assign d = Q[01 endrodule The module count4 counts in a special way. 8. What is the next output Q[310[2]Q[1jQ[0] after 0000? A. O 0001 B. O 0011 C. O 1100 D. 0010 E. 00110 9. In the above question, What is the next output Q[3]Q[2]Qt1jQ[0] after 0110? (Be careful that the leftmost bit in the answer is Q[3] and the rightmost bit is Q[0].) A. 0010 B. 1001 C. O 1100 D. 00000 E. O 0110

Explanation / Answer

8.

If Q[3]Q[2]Q[1]Q[0] is 0000
assign a = ~Q[1];
assign b = ~Q[2];
assign c = Q[3];
assign d = Q[0];

Then a = 1 , b = 1 , c = 0, d = 0

Then Q[3]Q[2]Q[1]Q[0] is dcba => 0011

Hence the answer is (B)

9.

We give the input

q[3]=d = 0, q[2]=c = 1 , q[1]=b = 1 and q[0]=a = 0

and pass them to 4 D flip flops named a,b,c,d i.e.0110

a = ~q[1] = 0 and pass it to Flip Flop A than next output q[1] = 0 ,/* According characterized table of d flip flop

if D=0 and q = 0 than qn is set to 0.*/

b = ~q[2] = 0 and pass it to flip flop B than q[2] = 1,/* D= 1, q = 0 so qn = 1*/
c = q[3] = 0 and pass it to flip flop c than q[3] = 0,/* D= 1, q=0 so qn =1*/
d = q[0] = 0 and pass it to flip flop c than q[0] = 0, /*D= 0, q=0 so qn =0*/

and get the next value i.e. q[3] q[2] q[1] q[0] = 1100.

The lines between the /* and */ are conditions for Characterized table of D flip flop corresponding to bit.

Hence the answer is (c).

Thankyou, i hope it helps you please like it.

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