5. In this exercise, we will explore the control unit for a cache controller for

Question

5. In this exercise, we will explore the control unit for a cache controller for a processor with a write buffer. Use the finite state machine found slide 129 as a starting point for designing your own finite state machines. Assume that the cache controller is for the simple direct-mapped cache described on slides 128-9, but you will add a write buffer with a capacity of one block. Recall that the purpose of a write buffer is to serve as temporary storage so that the rocessor doesn't have to wait for two memory accesses on a dirty miss. Rather than writing back the dirty block before reading the new block, it buffers the dirty block and immediately begins reading the new block. The dirty block can then be written to main memory while the processor is working. What should happen if the processor issues a request that hits in the cache while a block is being written back to main memory from the write buffer What should happen if the processor issues a request that misses in the cache while a block is being written back to main memory from the write buffer? a) b)

Explanation / Answer

a)What should happen if the processor issues a request that hitsin the cache while a block is being written back to main memory from the write buffer?

Answer:

The cache will be able to meet the request because otherwise it is idle when write buffer is writing back to memory. On the other hand when the cache is not able to meet hits while writingback from the buffer, the cache perform no better than the cache without the buffer. This is because the requests are still serialized behind the write backs.

(b) What should happen if the processor issues a request that missesin the cache while a block is being written back to main memory from the write buffer?

Answer:

The cache will need to wait until the write back is finished since the memory channel is occupied. Eventually when the memory channel is free then the cache will be allowed to issue the read request to satisfy the miss

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