Help with this Computer architecture problem? 3) (25 pts) The 4-Stage Pipeline b

Question

Help with this Computer architecture problem?

3) (25 pts) The 4-Stage Pipeline below suffers from the memory access resource conflict as shown below (instruction i and i+2 want to access memory at the same time and i+2 needs to be denied, so it waits for the next cycle; in the next cycle it has a conflict with i+1 so it stalls for another cycle). Is it there any speedup due to pipelining? [1] FI Fetch an instruction from memory (500 ps) 2] DA: Decode the instruction and calculate the effective address of the operand (400 ps) 3] FO: Fetch the operand (500 ps) [4] EX: Execute the operation (600 ps) With one memory, a data and an instruction fetch cannot be initiated in the same clock FIDA FO EX i+1 i+2 stall stall FIDA FO EX The Pipeline is stalled for resource conflict Two-port memory can serve without stalls

Explanation / Answer

Using pipeline 8 cycle is required. Where cycle time is max of pipeline stage i.e. 600 ps

So total time = 8*600 = 4800 ps

For non pipeline each execution require sane amount of time. i.e.

= 500+400+600+500 =2000 ps

For three instruction = 2000*3 =6000 ps

Speed up = 6000/4800 =1.25 times.

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