Computer architecture lab: Can you please provide me the vhdl code for this and

Question

Computer architecture lab: Can you please provide me the vhdl code for this and few test benches. Thank you

Design ROM that has 16 locations each 32 bits wide. The 16 locations have the values like OxDEADBE 0xCAFEBABE, 0xDEADFEED and so on of your choice. There will be a Chip Select (CS) input that activates the chip. The address input to the chip is a vector. The output would also be a vector that should send out the data already initialized at the active clock edge, depending on the address input to the chip. Clk CS Address Data Out ROM 16x32 bits The interface can be as below: entity ROM_32Bits_Design is port( Clk:instd logic CS:instd logic Address:instd logic_vector (3downto0) Data_Out:outstd_logic_vector (31downto0) 2. Pre-lab Study and analyze the working of a ROM Study how to do the type conversion in VHDL: * . std logic vectorsigned/unsigned . signed/unsigned integer . std_logic_vector?integer

Explanation / Answer

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
entity sram is
Port
(clk, Reset, run : IN std_logic;
adc_full, data_over : IN std_logic;
data : IN std_logic_vector (7 downto 0);
ADCout : OUT std_logic_vector(7 downto 0));
end sram;
ARCHITECTURE Behavorial OF sram IS
signal adccount, datacount : integer range 0 to 7 := 0;
--CONSTANT word_limit : integer := 15;
type mem_type is array (0 to 7) of std_logic_vector(7 downto 0);
signal ADC_array : mem_type :=
( 0 => "00010000",
1 => "00010001",
2 => "00010010",
3 => "00010011",
4 => "00010100",
5 => "00010101",
6 => "00010110",
7 => "00010111");
BEGIN
process(clk)
begin
if (Reset = '1') then
adccount <= 0;
elsif (rising_edge(clk)) then
if (adc_full = '1') then
adccount <= adccount + 1;
end if;
ADC_array(adccount) <= data ;
end if;
if (adccount = 8) then
adccount <= 0;
end if;
--read the data
datacount <= 1;
if (rising_edge(clk)) then
if (data_over = '1') then
datacount <= datacount + 1;
end if;
ADCout <= ADC_array(datacount);
end if;
if (datacount = 8) then
datacount <= 0;
end if;
end process;
END Behavorial;

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