Can you please write a VHDL testbench code for the below lab. II RAM Design 1. R

Question

Can you please write a VHDL testbench code for the below lab. II RAM Design 1. Requirement Write VHDL code for a RAM that has 16 locations each 32 bits wide. There will be a Chip Select (CS) input that activates the chip. Another input to the circuit is an R/W which determines if the read or a write to the chip. The address input to the chip is a vector. The input and output would also be a vector(s) that should send and receive the data, depending on the address input to the chip operation is a Clk CS Address Data Out RAM 16x32 bits R/W Data In The interface can be declared as below: entity RAM 32Bits is port( Clk:instd logic cs:instd logic: R W:instd logic; Address instd logic vector (3downtoD) Data In:instd logic vector (31downto) Data Out:outstd logic vector (31 downto)

Explanation / Answer

VHDL Code for RAM Design:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity RAM_32Bits is
port (
Clk: in std_logic;
CS: in std_logic;
RW: in std_logic;
Address: in std_logic_vector(3 downto 0);
Data_In: in std_logic_vector(31downto 0);
Data_Out: out std_logic_vector(31downto 0);
)
end entity RAM_32Bits;

architecture RAM_32 of RAM_32Bits is

// Declare Memory Array
type RAM is array (3 downto 0) of std_logic_vector(31 downto 0);
signal mem_array: ram;

// Signal Declaration
signal read_addr: std_logic_vector (3 downto 0);

begin

process (Clk)
begin
if (Clk’event and Clk=’1’) then
if (CS=’1’ and RW=’1’) then
ram(conv_integer(Address)) <= Data_In;
endif;
if (CS=’1’ and RW=’0’) then
read_addr <= Address;
endif;
else
read_addr <= read_addr;
endif;
endprocess

Data_Out <= ram[conv_integer(read_addr)];

end architecture RAM_32;

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