[VERILOG] Design a 2-input 32-bit multiplexor and a 2-input 5-bit multiplexor. U

Question

[VERILOG]

Design a 2-input 32-bit multiplexor and a 2-input 5-bit multiplexor. Use "switch" or "if-then-else" statement. Submit your verilog code and explain the waveform used for testing. (You can use "assign" statements within always block.)

The module must have the following format.

module Mux32Bit2To1(a, b, op, result);

input [31:0] a, b; // 32-bit inputs

input op; // one-bit selection input

output [31:0] result; // 32-bit output

module Mux5Bit2To1(a, b, op, result);

input [4:0] a, b; // 5-bit inputs

input op; // one-bit selection input

output [4:0] result; // 5-bit output

Explanation / Answer

Mux32Bit2To1.v

=============================================================

Mux5Bit2To1.v

Related Questions

Navigate

• Browse (All)
• Browse #
• Subjects

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.