Modify the VHDL Architecture for the 74LS112 J-K flip-flop so that the preset (P

Question

Modify the VHDL Architecture for the 74LS112 J-K flip-flop so that the preset (PRE) is synchronous instead of asynchronous. The clear (CLR) remains asynchronous. ENTITY jkflipflop IS PORT( J, K, PRE, CLR, CLOCK :IN BIT; Q,QN :BUFFER BIT); END jkflipflop; ARCHITECTURE behavior OF jkflipflop is BEGIN PROCESS (CLOCK, CLR, PRE) BEGIN IF (CLR = '0') THEN Q <= '0'; QN <= '1'; ELSIF (PRE = '0') THEN Q <= '1'; QN <= '0'; ELSIF (J = '0' and K = '0') then Q <=Q; QN <=QN; elsif(J = '0' and K = '1') then Q <= '1'; QN <= '0'; elsif(J = '1' and K = '0') then Q <= '0'; QN <= '1'; elsif(J = '1' and K = '1') then Q <= NOT Q; QN <= NOT QN; END IF; END PROCESS; END behavior;

Explanation / Answer

ENTITY jkflipflop IS PORT( J, K, PRE, CLR, CLOCK :IN BIT; Q,QN :BUFFER BIT); END jkflipflop; ARCHITECTURE behavior OF jkflipflop is BEGIN PROCESS (CLOCK, CLR or PRE) BEGIN IF (CLR = '0') THEN Q

Related Questions

Navigate

• Browse (All)
• Browse M
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.