In estimating the performance of the single cycle MIPS implementation, we assume

Question

In estimating the performance of the single cycle MIPS implementation, we assumed that only the major functional units had any delay (i.e. the delay of the multiplexers, the control units, PC access, sign extension unit, and wires are negligible). Assume that the actual time taken by each component in the architecture is as follows: Instruction Memory fetch (200 ps). Register read (100 ps). ALU operation (200 ps). Data access (300 ps) and Register write (100 ps) where ps stands for pico-seconds (1 ps = 1 times 10-12 seconds). Assume that we use different types of adders to implement addition for different functions. The delays of each type of adder are specified as follows: Answer the following questions: What would the cycle time be if X=300 and Y=300? What would the cycle time be if X=500 and Y=500? What would the cycle time be if X=100 and Y=800?

Explanation / Answer

In a single cycle MIPS Implementation, Cycle time is taken as the time taken for the longest instruction to execute. So , in general , (i.e, if all the adders have same delays) the instruction "lw"(load word) takes longest time compared to all other instructions. Time for lw= time(memory fetch) + time(register read) + time(ALU operation) + time(Data access) + time(register write) = 200+100+200+300+100 = 900 ps (Here PC+4 is done during the Data Access and register write )So above time is true if time(Data access)+time(register write) >time(adder for PC+4) (i.e, 300+100 >X) So in case a) X=300 < 400 so cycle time = 900ps b) X=500 >400 so cycle time = 900-400+500 =1000 ps c) In this case branch instruction becomes longest because of time(branch address computation) is far greater than time(Data access)+time(register write) time(branch instruction) = time(memory fetch) + time(register read) + time(ALU operation) +time(branch address calculation) = 200+100+200+800 = 1300ps. so cycle time in case c) is 1300ps.

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