module pro2(aIn, bIn ,cIn, sIn, bOut, cOut, clk); parameter n=3; input [n-1:0] a
ID: 656674 • Letter: M
Question
module pro2(aIn, bIn ,cIn, sIn, bOut, cOut, clk);
parameter n=3;
input [n-1:0] aIn;
input [n-1:0] bIn;
input [n:0] sIn;
input cIn, clk;
output [n-1:0] bOut;
output cOut;
reg cOut;
reg[n-1:0] bOut;
reg [n:0]tmp;
always @(negedge clk)
begin
cOut = 1'b0;
case (sIn)
0:bOut = ~aIn;
1:bOut = ~(aIn | bIn);
2:bOut = ~aIn & bIn;
3:bOut = 0;
4:bOut = ~(aIn & bIn);
5:bOut = ~bIn;
6:bOut = aIn^bIn;
7:bOut = aIn & ~bIn;
8:bOut = ~aIn | bIn;
9:begin
tmp = {1'b0,aIn} + {1'b0,bIn};
bOut = tmp[n-1:0];
cOut = tmp[n];
end
10:begin
tmp = {1'b0,aIn} + {1'b0,bIn} + {8'b0, cIn};
bOut = tmp[n-1:0];
cOut = tmp[n];
end
11:begin
tmp = {1'b0,aIn} - {1'b0,bIn};
cOut = tmp[n];
end
12:begin
tmp = {1'b0,aIn} - {1'b0,bIn} - {7'b0, cIn};
bOut = tmp[n-1:0];
cOut = tmp[n];
end
13:bOut = ~(aIn ^bIn);
14:bOut = -aIn;
15:bOut = 4'b1;
endcase
?case (15) // Birthday Function 0 > 6 > 2 > 7 > 9 > 2
??wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10;
??and A1(w1, ~sIn, ~aIn, ~cIn);
??and A2(w2, ~bIn, ~cIn);
??and A3(w3, sIn, aIn, bIn);
??or O1(w4, w1, w2, w3);
??and A4(w5, ~bIn, cIn);
??and A5(w6, bIn, ~cIn);
??or O2(w7, w5, w6);
??and A6(w8, ~bIn, cIn);
??and A7(w9, bIn, cIn);
??or O3(w10, w8, w9);
??or O4(Y, w4, w7, w10);
end
endmodule
PIN PLANNER:
Clk
Create a Verilog program for the Deo-Nano hoard which will create an ALU that has a 4-bit select function (16 total functions) and operates on two 3-bit registers. It produces a 3-b.t output plus a carry bit. The output should only change on the falling edge on a clock signal. The 3-bit output should use the LEDs on the Dco-Nano board. Use LEDO as the l-SB and LED2 as the MSB. Use LED3 as the carry bit. For this ALU you will have the following I/O connections. A) Use KEYO (push button) as the clock input. B) Both 3-bit inputs from the GPIO pins. Choose any 6 GPIO pins. C) The 4-bit input for the select lines from the onboard dip switches. D) 4 on board LEDs for output. Use LEDO though LED02 as the outputs with LEDO being the LSB. Use LED3 as the carry out. All of the requirements for B-level project must be met with the following additions: Function "15" should be to output your birthday in the following sequence- Day/Month/Year. For example, if your birthday is February 7. 1996 your circuit should display 0rightarrow7rightarrow0rightarrow2rightarrow9rightarrow6rightarrowrepeat. The output number should change once per clock cycle. The clock should come from a function generator set to 1 Hz and fed in through one of the GPIO pins instead of coming from KEYO. To connect the GPIO pins you will need to get six or seven connecter wires from Jeff in the stockroom so that you can make connections without soldering. Due to the number of boards available, students must work in groups of 2. The code for the project can be developed cooperatively. However, each student write his/her own code and lead it before demonstrating the functionality of the hardware. Turn in the following: 1. A cover sheet with your teams names, project name, and the date turned in 2. A photo of your board and connections. 3. A complete commented Verilog code for your ALU design. 4. A list of operations which you performed on your board along with the results and -.n indication of whether or not the result was correct.Explanation / Answer
module pro2(aIn, bIn ,cIn, sIn, bOut, cOut, clk);
parameter n=3;
input [n-1:0] aIn;
input [n-1:0] bIn;
input [n:0] sIn;
input cIn, clk;
output [n-1:0] bOut;
output cOut;
reg cOut;
reg[n-1:0] bOut;
reg [n:0]tmp;
always @(negedge clk)
begin
cOut = 1'b0;
case (sIn)
0:bOut = ~aIn;
1:bOut = ~(aIn | bIn);
2:bOut = ~aIn & bIn;
3:bOut = ~aIn & bIn;
4:bOut = 0;
5:bOut = ~bIn;
6:bOut = aIn^bIn;
7:bOut = ~aIn & bIn
8:bOut = ~aIn | bIn;
9:begin
tmp = {1'b0,aIn} + {1'b0,bIn};
bOut = tmp[n-1:0];
cOut = tmp[n];
end
10:begin
tmp = {1'b0,aIn} + {1'b0,bIn} + {8'b0, cIn};
bOut = tmp[n-1:0];
cOut = tmp[n];
end
11:begin
tmp = {1'b0,aIn} - {1'b0,bIn};
cOut = tmp[n];
end
12:begin
tmp = {1'b0,aIn} - {1'b0,bIn} - {7'b0, cIn};
bOut = tmp[n-1:0];
cOut = tmp[n];
end
13:bOut = ~(aIn ^bIn);
14:bOut = -aIn;
15:bOut = 4'b1;
endcase
?case (15) // Birthday Function 0 > 7 > 0 > 4 > 9 > 2
??wire w1, w2, w3, w4, w5, w6, w7, w8, w9, w10;
??and A1(w1, ~sIn, ~aIn, ~cIn);
??and A2(w2, ~bIn, ~cIn);
??and A3(w3, sIn, aIn, bIn);
??or O1(w4, w1, w2, w3);
??and A4(w5, ~bIn, cIn);
??and A5(w6, bIn, ~cIn);
??or O2(w7, w5, w6);
??and A6(w8, ~bIn, cIn);
??and A7(w7, bIn, cIn);
??or O3(w6, w8, w9);
??or O4(Y, w4, w7, w6);
end
endmodule
PIN PLANNER:
Clk
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