You are designing an adder, built from three full adders such that the carry out

Question

You are designing an adder, built from three full adders such that the carry out of the first adder is the carry into the second adder, and the carry out of the second adder is the carry into the third adder, as shown in the figure. Your adder has input and output registers and must complete the addition in one clock cycle. Each full adder has the following propagation delays?: 20 ps from Cin to Cout or to Sum(S), 25 ps from A or B to Cout , and 30 ps from A or B to S. The adder has a contamination delay?of 15 ps from Cin to either output and 22 ps from A or B to either output. Each flip

Explanation / Answer

a) If there is no clock skew, what is the maximum operating frequency of the circuit?

Tc?Tpcq + Tpd + Tsetup
   =35+3*35+30
   =35+105+30
   =170

Max Frequency = 1/Tc =1/170=5.8 Ghz

b)

Tc?Tpcq + 2*Tpd + Tsetup + Tskew

Tc?135 + Tskew

Tccq + 2Tcd?Thold +Tskew
Tskew<=52ps

c)

Tccq + Tcd?Thold + Tskew

Shortest Path:

Tccq + Tcd?Thold + Tskew
20+21?10+Tskew
Tskew<31ps

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