So I saw this question was asked before some time ago on this site, buuuut never

Question

So I saw this question was asked before some time ago on this site, buuuut never got a proper answer and I want to see if I'm doing it right. so here 'goes:

Your memory hierarchy is arranged as described in the Table below. The access main memory is 50ns and the benchmark is comprised of 40% memory accesses. The clock period of the machine is 0.5ns.

Cache Parameters:

1. Describe what happens on a write miss in the L1 (i.e. you execute a SW instruction and the destination address is not present in the L1 cache).

2. What is the AMAT of a machine with only an L1 cache?

3. What is the AMAT of a machine with both L1 and L2 caches?

4. What is the total CPI of the machine with both caches? Assume a base CPI of 1.

Any help would be greatly appreciated. Thanks.

L1 L2 Size 32 kB 2 MB Line Size 32 B 32 B Associativity 2-Way SA 16-way SA Write Policy Write-back Write-through Allocation Policty Write allocate No-write allocate Access Time 0.5 ns 2 ns Hit Rate 42% 80%

Explanation / Answer

1.

When a write miss occurs for a L1 cache, a line is blocked for writing the data into the cache. The write that is missed in the cache causes the block to be fetched from a lower level in the hierarchy of memory.

2.

Hit time for L1 cache = 0.95 ns

L1 miss rate =1-hit rate

                     = 1- 0.42

                     = 0.58 (or) 58%

Main memory access time = 50 ns.

Average Memory Access Time = (Hit time + (Miss rate * Miss penalty)

                                                   = 0.95 + (58%* 50)

                                                   = 0.95 + 29

                                                   = 29.95 ns.

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