Need help with these Verilog problems Problem 0: Run the testbench on the unmodi

Question

Need help with these Verilog problems

Problem 0: Run the testbench on the unmodified file. There should be errors on all but the min_4 (Four-element) module. Try modifying min_4 so that it simulates but produces the wrong answer. Re-run the simulator and verify that it’s broken. Then fix it.

Problem 1: Module min_n has an elt_bits-bit output elt_min and an elt_count element array of elt_bits-bit elements, elts. Complete min_n so that elt_min is set to the minimum of element in elts, interpreting the elements as unsigned integers. Do so using a linear connection of min_2 modules instantiated with a genvar loop. (A linear connection means that the output of instance i is connected to the input of instance i + 1.) Verify correct functioning using the testbench.

Problem 2: Module min_t is to have the same functionality as min_n. Complete min_t so that it recursively instantiates itself down to some minimum size. The actual comparison should be done by a min_2 module. Verify correct functioning using the testbench.

Problem 3: By default the synthesis script will synthesize each module for two array sizes, four elements and eight elements. (a) Run the synthesis script unmodified (use the command rc -files syn.tcl. Explain the differences in performance between the different modules. (b) Modify and re-run the synthesis script so that it synthesizes the modules with elt_bits set to 1. The synthesis program should do a better job on the behavioral and linear models. Why do you think that is? Hint: The 1-bit minimum module is equivalent to another common logic component that the synthesis program can handle well.

Here's the link to the verilog.

http://pastebin.com/HQDxK9kh

Any help would be appreicated. Thank you.

Explanation / Answer

module min_b
#( int elt_bits = 4,
int elt_count = 8 )
( output logic [elt_bits-1:0] elt_min,
input wire [elt_bits-1:0] elts[elt_count] );

always @* begin

elt_min = elts[0];

for ( int i=1; i<elt_count; i++ )
if ( elts[i] < elt_min ) elt_min = elts[i];

end

endmodule


/// Implicit Structural 2-Input Minimum Module
//
module min_2
#( int elt_bits = 4 )
( output wire [elt_bits-1:0] elt_min,
input wire [elt_bits-1:0] elt_0,
input wire [elt_bits-1:0] elt_1 );

assign elt_min = elt_0 < elt_1 ? elt_0 : elt_1;

endmodule

/// Explicit Structural 4-Input Minimum Module
//
module min_4
#( int elt_bits = 4 )
( output wire [elt_bits-1:0] elt_min,
input wire [elt_bits-1:0] elts [4] );

wire [elt_bits-1:0] im1, im2;
min_2 #(elt_bits) m1( im1, elts[0], elts[1] );
min_2 #(elt_bits) m2( im2, elts[2], elts[3] );
min_2 #(elt_bits) m3( elt_min, im1, im2 );

endmodule

//////////////////////////////////////////////////////////////////////////////
/// Problem 1
//
/// Linear Generate minimum module.
//
// Complete the module.
//
// [ ] Use a generate loop.
// [ ] The code must be synthesizable.
// [ ] Make sure that the testbench does not report errors.

module min_n
#( int elt_bits = 4,
int elt_count = 8 )
( output wire [elt_bits-1:0] elt_min,
input [elt_bits-1:0] elts [ elt_count ] );

/// Replace module below with solution.

min_2 #(elt_bits) m( elt_min, elts[0], elts[1] );

endmodule


//////////////////////////////////////////////////////////////////////////////
/// Problem 2
//
/// Tree Generate minimum module.
//
// Complete the module.
//
// [ ] Use recursion: the module should instantiate itself or a min_2.
// [ ] The code must be synthesizable.
// [ ] Make sure that the testbench does not report errors.


module min_t
#( int elt_bits = 4,
int elt_count = 8 )
( output wire [elt_bits-1:0] elt_min,
input [elt_bits-1:0] elts [ elt_count-1:0 ] );

/// Replace module below with solution.

min_2 #(elt_bits) m( elt_min, elts[0], elts[1] );

endmodule


//////////////////////////////////////////////////////////////////////////////
/// Testbench Code
//
// The code below instantiates some of the modules above,
// provides test inputs, and verifies the outputs.
//
// The testbench may be modified to facilitate your solution. Of
// course, the removal of tests which your module fails is not a
// method of fixing a broken module. (The idea is to put in tests
// which make it easier to determine what the problem is, for
// example, test inputs that are all 0's or all 1's.)


// cadence translate_off

module testbench;

testbench_sz #(1,4) t0();
testbench_sz #(4,4) t1();
testbench_sz #(8,32) t2();
testbench_sz #(7,17) t3();

endmodule

module testbench_sz
#( int elt_bits = 8,
int elt_count = 80 );

localparam int mut_cnt_max = 5;

logic [elt_bits-1:0] elts[elt_count];

wire [elt_bits-1:0] elt_m[mut_cnt_max];
struct { int err_cnt = 0; int idx; } md[string];

min_b #(elt_bits,elt_count) m0(elt_m[0],elts);
min_n #(elt_bits,elt_count) m1(elt_m[1],elts);
if ( elt_count == 4 )
min_4 #(elt_bits) m2(elt_m[2],elts);

min_t #(elt_bits,elt_count) m3(elt_m[3],elts);

localparam int num_tests = 10000;

initial begin

md["Linear Generate"].idx = 1;
md["Tree Generate"].idx = 3;
if ( elt_count == 4 )
md["Four-Element"].idx = 2;

for ( int i=0; i<num_tests; i++ ) begin

for ( int j=0; j<elt_count; j++ ) elts[j] = $random();

#1;

foreach ( md[mut] ) begin

if ( elt_m[0] !== elt_m[md[mut].idx] ) begin

md[mut].err_cnt++;
if ( md[mut].err_cnt < 5 )
$write("Error test %0d for %s, 0x%x != 0x%x (correct) ",
i, mut, elt_m[md[mut].idx], elt_m[0] );
end

end

end

foreach ( md[mut] )
$write("Tests completed for %s at %0d x %0d, error count %0d ",
mut, elt_bits, elt_count, md[mut].err_cnt );

end

endmodule

// cadence translate_on

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