Using this diagram do the following: (a) Write a VHDL module for a 4-bit adder,
ID: 669169 • Letter: U
Question
Using this diagram do the following:
(a) Write a VHDL module for a 4-bit adder, with a carry-in and carry-out, using an overloaded addition operator and std_logic_vector inputs and outputs.
(b) Design an 8-bit subtracter with a borrow-out, using two of the 4-bit adders you designed in (a), along with any necessary gates or inverters. Write a VHDL module for the subtracter.
(c) Simulate your code and test it using the following inputs:
11011011 – 01110110, 01110110 – 11011011
Explanation / Answer
a)
library ieee;
use ieee.std_logic_1164.all;
entity adder4 is
port
( A: in std_logic_vector(3 downto 0);
B: in std_logic_vector(3 downto 0);
CI: in std_logic;
O: out std_logic_vector(3 downto 0);
CO: out std_logic
);
end entity adder4;
component fulladder is
port
( A: in std_logic;
B: in std_logic;
CI: in std_logic;
O: out std_logic;
CO: out std_logic
);
end component fulladder;
signal carry_internal: std_logic_vector(4 downto 0);
begin adders: for N in 0 to 3
generate myfulladder: fulladder
port map
( A => A(N),
B => B(N),
CI => carry_internal(N),
CO => carry_internal(N+1)
);
end generate;
carry_internal(0) <= CI;
CO <= carry_internal(4);
end behave;
b)
subtractor code is same as shown in diagram above.
replicate the adder code twice
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