Processor Hardware Design - MIPS Given this processor hardware design and the co

Question

Processor Hardware Design - MIPS

Given this processor hardware design and the control sequence below, describe in words (or C-like pseudo code) the function of the instruction xyzzy $rt, $rs. when op() op(l) Xyzzy Start: PCout, HARin, MEMread, Yin CONST(4), ALUadd, Zin, UNTILmfc MDRoutj IRin Zout, PCin, DUMPonop HALT/* Should end here on undecoded op */ Xyzzy: CONST(-1), Yin SELrs, REGout, ALUxor, Zin Zout, SELrt, REGin, JUMP(Start) Given the xyzzy $rt,$rs instruction as defined above, and assuming that a memory load request takes 4 clock cycles to complete (after MEMread has been issued), how many clock cycles would it take to execute each xyzzy instruction? You may use the simulator to get or check your answer. In any case, give and briefly explain your answer here:

Explanation / Answer

6.

rd=rd+rd;

7.

We pass through 4 states to decode the instruction and 6 to execute it... but there are UNTILmfc delays.

Both times, the UNTILmfc comes immediately after the MEMread, so that state is repeated 3 more times.

Then, 4+3+6+3=16 CPI

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