According to its design specification, the timer circuit delaying the closing of

Question

According to its design specification, the timer circuit delaying the closing of an elevator door is to have a capacitance of 31.0 µF between two points A and B. When one circuit is being constructed, the inexpensive but durable capacitor installed between these two points is found to have capacitance 34.0 µF. To meet the specification, one additional capacitor can be placed between the two points.

(a) Should it be in series or in parallel with the 34.0 µF capacitor?

in seriesin parallel     

(b) What should be its capacitance?
µF

(c) The next circuit comes down the assembly line with capacitance 30.1 µF between A and B. To meet the specification, what additional capacitor should be installed in series or in parallel in that circuit?

Explanation / Answer

Here ,

a)
as the equivalent capacitor is higher than the indivisual capacitance

the capacitance should be in parallel

b)let the capacitance needed in series is C

Now , for Ceq = 34 uF

in parallel

Ceq = C + C1

34 = 31 + C1

C1 = 3 uF

the capacitance should be 3 uF

c)

Now , capacitance , 30.1 uF in series

additional capacitance ,

C + 1/(1/30.1 + 1/34) = 34

C = 18.3 uF

additional capacitance should be 18.3 uF in parallel

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