A logic-circuit family with zero static power dissipation normally operates at V

Question

A logic-circuit family with zero static power dissipation normally operates at VDD = 2.5V. To reduce its dynamic power dissipation, operation at 1.8V is considered. It is found, however, that the currents available to charge and discharge load capacitances also decrease.

If current is:

(a) proportional to VDD or (b) proportional to VDD2

THEN:

1. What reductions in maximum operating frequency do you expect in each case?

2. What fractional change in delay-power product do you expect in each case?

Please Note: This is all that is provided in the question. No supplementary tables, graphs, or schematics.

Explanation / Answer

Case: a)

current is proportional to VDD1=1.8V

By lowering the supply voltage, is effective in reducing power dissipation.

Lowering the supply voltage restricts the operating frequency accordingly because,

fclk [(VDD - Vt) 2 / VDD )]

Vt = 1V

1)

for VDD=2.5V :

fclk [(VDD - Vt) 2 / VDD )] = [(2.5-1)2/2.5]= 0.9

fclk=0.9f

for VDD1 =1.8V :

fclk1 [(VDD1- Vt) 2 / VDD1)] = [(1.8-1)2/1.8]= 0.35

fclk1=0.35f

reduction in operating frequency fr=fclk-flck1 = 0.9f-0.35f=0.55f [ANSWER]

2)

Pdynmaic CL VDD2 fclk

Delay t   1/fclk

Delay Power Product(DPP) = Delay x Pdynmaic    CL VDD2 fclk x 1/fclk = CL VDD2

For VDD=2.5 V fclk=0.9f

Delay Power Product(DPP) = Delay x Pdynmaic CL VDD2 = CL 2.52=6.25 x CL

For VDD1=1.8 V fclk1=0.35f

Delay Power Product(DPP1) = Delay x Pdynmaic1 CL VDD12 = CL 1.82=3.24 x CL

Reduction in dynamic delay power product is DPP0=DPP-DPP1 =(6.25-3.24 )x CL = 3.01 x CL [ANSWER]

CASE :b)

current is proportional to VDD2=2V

By lowering the supply voltage, is effective in reducing power dissipation.

Lowering the supply voltage restricts the operating frequency accordingly because,

fclk [(VDD - Vt) 2 / VDD )]

Vt = 1V

1)

for VDD2 =2V :

fclk2 [(VDD2- Vt) 2 / VDD2)] = [(2-1)2/2]= 0.5

fclk2=0.5f

reduction in operating frequency fr=fclk-flck2 = 0.9f-0.5f=0.4f [ANSWER]

2)

Pdynmaic CL VDD2 fclk

Delay t   1/fclk

Delay Power Product(DPP) = Delay x Pdynmaic    CL VDD2 fclk x 1/fclk = CL VDD2

For VDD2=2 V fclk1=0.5f

Delay Power Product(DPP2) = Delay x Pdynmaic2 CL VDD22 = CL 22=4 x CL

Reduction in dynamic delay power product is DPP0=DPP-DPP1 =(6.25-4 )x CL = 2.25 x CL [ANSWER]

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