IP Core (Named alu4_ip): Design an ALU (see Figure 1) using IP Coregen to create

Question

IP Core (Named alu4_ip): Design an ALU (see Figure 1) using IP Coregen to create the 4-bit adder and subtractor unit(s).

Design Constraints: The design must properly function given the following constraints:

- The A input is named A_in and is 4 bits wide.

- The B input is named B_in and is 4 bits wide.

- The Select input is named SEL_in and is 2 bits wide.

- For the Structural models, you may only use the behavioral components you created (adder, inverter, mux, etc) or Verilog Primitives.

I am using Verilog code software, so if possible I would like the answer to be in that format. Thanks

Explanation / Answer

module alu (ans,a,b,sel);

output reg [3:0] ans;     //output of alu
   input [3:0] a,b;    //inputs to alu
   input [1:0] sel;//control signal for alu
   always @(*)
    begin
    case (sel)
    2'b00 : begin op = ~a; $display("NOT operation"); end
    2'b01 : begin op = a + b; $display("Addition operation"); end
    2'b10 : begin op = a - b; $display("Subtraction operation"); end
    2'b11 : begin op = a<<1; $display("1 bit shift left operation or multiply by 2"); end
    endcase
    end
endmodule

Related Questions

Navigate

• Browse (All)
• Browse I
• Subjects

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.