IP Core (Named alu4_ip): Design an ALU (see Figure 1) using IP Coregen to create
ID: 3663749 • Letter: I
Question
IP Core (Named alu4_ip): Design an ALU (see Figure 1) using IP Coregen to create the 4-bit adder and subtractor unit(s).
Design Constraints: The design must properly function given the following constraints:
- The A input is named A_in and is 4 bits wide.
- The B input is named B_in and is 4 bits wide.
- The Select input is named SEL_in and is 2 bits wide.
- For the Structural models, you may only use the behavioral components you created (adder, inverter, mux, etc) or Verilog Primitives.
Select (S) Si SO Function S S0 Invert Add Subtract Double ALU A+B A-B 12 A Figure 1: ALU Port Interface and Function TableExplanation / Answer
the correct answer is
Demonstrating the ALU
In order to easily see the output of the ALU for the demo, you will display the results on 4
seven-segment displays and the LEDs.
1. Take as input two 4-bit 2's complement values from the board's switches, using the
push buttons to select which operation to perform. The switches will not be able to
test all possible situations, but at least most of them. You will need to sign-extend the
4-bit input values to the full 8-bits.
2. Produce an 8-bit value from the ALU, on the right three 7-segment displays with the
left blank for non-negative values and showing a '-' for negative. Use also the 8
LED’s on the extension board to display O[7:0], and the main board LEDs to display
ERR and Overflow.
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