Hello, I need some help figuring out my verilog code for a 4 bit asynchronous up

Question

Hello, I need some help figuring out my verilog code for a 4 bit asynchronous up counter. Here is a link to my code on edaplayground.com: http://www.edaplayground.com/x/VTn. All of the components seem to work just fine on their own, but once I try to combine them the output just produces xxxx for the four bit output. I'm sure its some simple little syntactical error or something.

Thanks for the help. I forgot to mention we're required to use structural code( ie. only using gate primitives ) im sure theres easier ways to do this.

Explanation / Answer

module counter (C, CLR, Q);
input C, CLR;
output [3:0] Q;
reg [3:0] tmp;

  always @(posedge C or posedge CLR)
    begin
      if (CLR)
        tmp = 4'b0000;
      else
        tmp = tmp + 1'b1;
      end
  assign Q = tmp;
endmodule

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