For questions 1-4 assume an 8 bit processor with a 24 bit address bus running a

Question

For questions 1-4 assume an 8 bit processor with a 24 bit address bus running a two megahertz clock. Also assume that each instruction is 1 byte long and each bus cycle takes three clock cycles to complete. The processor uses a von Neumann design and has only memory space. The reset address for the processor is FFF000. The only control signals available are /RD (low active) and /WR (low active.) 1. What is the maximum data rate on the bus for this processor? 2. How much memory (in bytes) can this processor support? 3. Given a block move instruction (BMOV), that tells the processor to copy a block of up to 256 bytes from one one location in memory to another where each location and the size of the block is specified using immediate addressing in the following format: BMOV Fromlocation, Tolocation, Blocksize The instruction BMOV OOFFFFH, 100000H, 10H instructs the processor to copy 16 bytes starting at address OOFFFFH to address starting at 100000H. The instruction is located starting at address FF0000H and assembles to machine code (HEX): 64 00 FF FF 10 00 00 10 3a. How many bus cycles will this instruction take to execute? 3b. List the sequence of bus cycles. 3c. For the first 12 bus cycles show what value is in the IP, IR, and MAR register 3d. Draw a memory map showing the instruction in memory and the affected blocks of memory before and after execution of the instruction. (You can assume any values you want in the block to be moved.) 3e. Draw the fetch bus cycle and first two operand read cycles. 3f Using the data from the memory map 3d draw out the 9th through 13th bus cycle

Explanation / Answer

a)

Since the clock frequency is 2MHz

and a write or read instruction takes 3clock cycles

=> maximum data rate = 2M/3=0.66Mbits

b)

since the addresss bus is 24bit ,

it can support 224 bits = 24Mbits = 2Mbytes

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