1. In a single .v file, write modules for the following state elements a. Gated
ID: 1717081 • Letter: 1
Question
1. In a single .v file, write modules for the following state elements a. Gated RS-latch (Structural) b. Negative edge-triggered JK Flip-Flop (Behavioral) c. Negative edge-triggered D-Flip-Flop with asynchronous reset and synchronous enable (Behavioral) d. A positive edge-triggered D-Flip-Flop implemented structurally in the Master-Slave pattern using D-latches (each D-latch, Behaviorally implemented). 2. Write a single testbench that goes through sufficient input patterns to showcase the behavioral differences of the above using the following paradigms (see testbench for sim3 for additional examples). Assume that the R and K inputs of elements a. and b. are the same, as are the J and S inputs. Similarly, assume that the D input is the same for c. and d. Create a module named Top that instantiates state elements a. through d. and tests them in parallel, driving their outputs to its outputs. Testbench paradigms: a. Clock generation via reg clkSlow; reg clkFast; always #7 clkSlow = ~clkSlow; always #2 clkFast = ~clkFast; b. Use a behavioral unconditional modulo up-counter with reset to keep track of time: reg [7:0] count; always@(posedge clkFast) begin if (reset) count <= 8’h00; else count <= count +8’h01; end c. Use clkSlow as the clock for all clocked/gated logic elements from task 1. Use the counter driven by clkFast and comparators to force events to happen at a specific time in the test case or directly connect bits of count to inputs.
Explanation / Answer
1) Verilog .V files
a) Gated RS latch:
module rslatch(
input clk,S,R,
output Q,Q_not
);
wire top1, bot1, Qback, notQback;
nand G1(top1,S, clk );
nand G2(bot1,clk, R );
nand G3(Qback,top1, notQback );
nand G4(notQback,Qback, bot1 );
assign Q = Qback;
assign Q_not = notQback;
endmodule
b) Negative Edge Triggered JK flipflop:
module jkff(
input J,K,CLK,
output Q,Q_not
);
reg Q;
reg Q_not;
always @(negedge clk)
if(J == 1 && K == 0)
begin
Q = 1;
Q_not=0;
end
else if(J == 0 && K == 1)
begin
Q = 0;
Q_not =1;
end
else if(J == 1 && K == 1)
begin
Q = ~Q;
Q_not = ~Q_not;
end
else
begin
Q = Q ;
Q_not = Q_not;
end
endmodule
3)Negative edge-triggered D-Flip-Flop with asynchronous reset and synchronous enable:
module d_ff(
input clk,rst,en,d,
output Q,Q_not
);
always@(negedge clk,posedge rst )
begin
if ((!rst_n)&en)
q <= 1'b0;
else
q <= d;
end
endmodule
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