Name: Section Number: Lab by jeg/modified by jec 4450:220 DIGITAL LOGIC DESIGN,

Question

Name: Section Number: Lab by jeg/modified by jec 4450:220 DIGITAL LOGIC DESIGN, Spring 2018 Pre-Lab 7: Counters and Timers Week Eight Objectives To learn about binary and decade counters, and to design a one-hundred second timer. The Counter A counter is a hardware circuit whose output counts in sequence, changing at each rising has a three-bit out rolls over" back to zero to count through the sequence again. We can d edge of a clock input signal. As an example, consider a three-bit binary up counter. It ion of the counter using a state diagram, where each arrow depicts the change of funct state that happens on the rising edge of the clock. Each circle represents the state of the hardware for one clock cycle; it shows both the count stored in the flip-flops during that clock cycle, and an output called Cout that is '1' in the clock cycle when the counter is about to "roll over" to zero. 000, Cout 001 010, 110, 101 011, 100, In hardware, this counter consists of three flip-flops, one to hold each bit of the count, plus some combinational logic (made from gates) to determine what state of the flip-flops should be next, given the current state. Some additional combinational logic determines the Cout output, given the current state.

Explanation / Answer

1. Period = 1/4 MHz =1/(4 x 106) = 250ns

2. Decade Counter have 10 states (i.e. 0 - 9). Hence 10 clock ticks count through the pattern once. Total time taken will be 10 times of clock period. 10 x 250ns = 2.5 microseconds

3. Total number of clock periods in 1 s = 1s/1 clock period

= 1s / 250ns = 4000000 = 4x106 clock periods

4. As shown in above solution, 4000000 ticks of clock needed to have 1 second delay. (4000000)10 = (1111010000100100000000)2. Hence for 22 bit number , 22 flip flops will be required

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