4. (a) Draw the circuit corresponding to Verilog module hw4_4a below. (b) Draw t

Question

4. (a) Draw the circuit corresponding to Verilog module hw4_4a below.
(b) Draw the circuit corresponding to Verilog module hw4_4b below. In this drawing,
represent module hw4_4a as a box with 3 inputs and 1 output as shown below.
module hw4_4a(x, y, z, f);
input x, y, z;
output f;
wire d, e;
assign d = (x | y);
assign e = (x & ~z) | (~x & z);
assign f = (d & e);
endmodule
module hw4_4b(A, B, c, G);
input [2:0] A, B;
input c;
output [2:0] G;
hw4_4a fold0 (c, A[0], B[0], G[0]);
hw4_4a fold1 (G[0], A[1], B[1], G[1]);
hw4_4a fold2 (G[0], B[2], A[2], G[2]);
endmodule

5. Consider the function g= ab + a'c + a'bc'. Use the truth table to derive a circuit for f
that uses a 2-to-1 multiplexer.

Explanation / Answer

The connector pins are TDI (Test Data In) TDO (Test Data Out) TCK (Test Clock) TMS (Test Mode Select) TRST (Test Reset) optional. Test reset signal is not shown in the image. The TRST pin is an optional active-low reset to the test logic - usually asynchronous, but sometimes synchronous, depending on the chip. If the pin is not available, the test logic can be reset by switching to the reset state synchronously, using TCK and TMS. Note that resetting test logic doesn't necessarily imply resetting anything else. There are generally some processor-specific JTAG operations which can reset all or part of the chip being debugged. Since only one data line is available, the protocol is serial. The clock input is at the TCK pin. One bit of data is transferred in from TDI, and out to TDO per TCK rising clock edge. Different instructions can be loaded. Instructions for typical ICs might read the chip ID, sample input pins, drive (or float) output pins, manipulate chip functions, or bypass (pipe TDI to TDO to logically shorten chains of multiple chips). As with any clocked signal, data presented to TDI must be valid for some chip-specific Setup time before and Hold time after the relevant (here, rising) clock edge. TDO data is valid for some chip-specific time after the falling edge of TCK. The maximum operating frequency of TCK varies depending on all chips in the chain (the lowest speed must be used), but it is typically 10-100 MHz (100-10 ns per bit). Also TCK frequencies depend on board layout and JTAG adapter capabilities and state. One chip might have a 40 MHz JTAG clock, but only if it's using a 200 MHz clock for non-JTAG operations; and it might need to use a much slower clock when it's in a low power mode. Accordingly, some JTAG adapters have adaptive clocking using an RTCK (Return TCK) signal. Faster TCK frequencies are most useful when JTAG is used to transfer lots of data, such as when storing a program executable into flash memory. Clocking changes on TMS steps through a standardized JTAG state machine. The JTAG state machine can reset, access an instruction register, or access data selected by the instruction register. JTAG platforms often add signals to the handful defined by the IEEE 1149.1 specification. A System Reset (SRST) signal is quite common, letting debuggers reset the whole system, not just the parts with JTAG support. Sometimes there are event signals used to trigger activity by the host or by the device being monitored through JTAG; or, perhaps, additional control lines. Even though few consumer products provide an explicit JTAG port connector, the connections are often available on the printed circuit board as a remnant from development prototyping and/or production. When exploited, these connections often provide the most viable means for reverse engineering.http://upload.wikimedia.org/wikipedia/commons/c/c9/Jtag_chain.svg

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