Olderversions of CMOS devices may have had input gate capacitances of 10pF, logi

Question

1. Olderversions of CMOS devices may have had input gate capacitances of 10pF, logic levels of 0-5V, and propagation delays of 10 ns. With smaller physical sizes, the same function might have an inputgate capacitance of 2 pF and operate at logic levels approaching0-1.5V. For a similar source and load impedance, estimate theincrease in speed and reduction in power for the newer devices as afunction of the speed and power of older devices.

Explanation / Answer

(a) The Speed (propagation delay ) in the simplest form is given by              Iavg = C(V)/tp => tp = CV/Iavg        Thus to a roughapproximation tp(new)/tp(old) = (CV/Iavg)new / (CV/Iavg)old         For CMOS device assuminga full swing in Voltage i.e. VOH = VDD and VOL = 0V we have Vnew = 1.5 V , and V old = 5 V Iavg = Isat = K1(VGS-VT)2 = K1(VDD-VT)2 (For larger physicalsize) For the newer devices Isat = K2(VGS-VT)2 = K2(VDD-VT)2 (For very small size devices Isat = K3(VGS-VT) =K3(VDD-VT) . However we don't consider that small sizeddevice for our analysis) where K1 and K2 are factors involving processparameters , and (W/L) ratio Assuming K1 and K2 are nearly equal and VDD-VT = VDD ( i.e, VT

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