Older versions of CMOS devices may have hadinput gate capacitances of 10 pF, log

Question

1. 1. Older versions of CMOS devices may have hadinput gate capacitances of 10 pF, logic levels of 0-5V, andpropagation delays of 10 ns.  With smaller physicalsizes, the same function might have an input gate capacitance of 2pF and operate at logic levels approaching 0-1.5V.  For asimilar source and load impedance, estimate the increase in speedand reduction in power for the newer devices as a function of thespeed and power of older devices.

1. Older versions of CMOS devices may have hadinput gate capacitances of 10 pF, logic levels of 0-5V, andpropagation delays of 10 ns.  With smaller physicalsizes, the same function might have an input gate capacitance of 2pF and operate at logic levels approaching 0-1.5V.  For asimilar source and load impedance, estimate the increase in speedand reduction in power for the newer devices as a function of thespeed and power of older devices.

Explanation / Answer

(a) The Speed (propagation delay ) in the simplest form is given by              Iavg = C(V)/tp => tp = CV/Iavg        Thus to a roughapproximation tp(new)/tp(old) = (CV/Iavg)new / (CV/Iavg)old         For CMOS device assuminga full swing in Voltage i.e. VOH = VDD and VOL = 0V we have Vnew = 1.5 V , and V old = 5 V Iavg = Isat = K1(VGS-VT)2 = K1(VDD-VT)2 (For larger physicalsize) For the newer devices Isat = K2(VGS-VT)2 = K2(VDD-VT)2 (For very small size devices Isat = K3(VGS-VT) =K3(VDD-VT) . However we don't consider that small sizeddevice for our analysis) where K1 and K2 are factors involving processparameters , and (W/L) ratio Assuming K1 and K2 are nearly equal and VDD-VT = VDD ( i.e, VT

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