Hi! I am taking a course where we use the programming language ofVHDL to program

Question

Hi! I am taking a course where we use the programming language ofVHDL to program digital circuits.
For an assignment, I have been asked to do the following:

PART1)
-Create a VHDL source file called Question1. This will also be thename for the entity.
-Declare the I/O by typing PORT(...) into the ENTITY declaration.Name the input signals D, and output signals Y. Declare them usingarrays.
-Compile
-Create a behavioral ARCHITECTURE using a PROCESS statements. Use aCASE statement in teh body to build the Truth Table.
-Run a syntax check and a simulation using ModelSim.

My question is if I wrote my code the way I have been asked to ,and I have difficulty in knowing which libraries I am supposed toimplement in my code...I did not know I had to use USEieee.numeric_std.ALL; for this one.

Any help will be much appreciated!!!!
Thank you in advance!

Explanation / Answer

You shouldn't need to use ieee.numeric_std.all because you arenot doing any type of conversion or arithmetic operations. I think the problem is that your declaring the CASE statementincorrectly. Instead of having your "entity" within the CASEstatement, it should be some type of signal. The best way to dothat is to do this: CASE D IS    WHEN      "0000"|"1110" =>             Y<= "0011";
    WHEN     "0011"|"1101" =>             Y<= "1100";
    WHEN      "0010"|"1001"=>             Y<= "0110";
    WHEN      "1000"=>             Y<= "1001";
    WHEN  OTHERS =>             Y <= "0000";
Also, it seems like your code has some syntax errors such assome semicolons, etc... HOPE THIS HELPS

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